BCA2050 COMPUTER ORGANIZATION

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(SPRING 2015) ASSIGNMENT

PROGRAM	BCA (Revised Fall 2012)
SEMESTER	2
SUBJECT CODE & NAME	BCA2050 COMPUTER ORGANIZATION
CREDIT	2
BK ID	B1642
MAX.MARKS	60

Note: Answer all questions. Kindly note that answers for 10 marks questions should be approximately of 400 words. Each question is followed by evaluation scheme.

1 What are the functions of Input and output devices?

Answer : The central processing unit is the unseen part of a computer system, and users are only dimly aware of it. But users are very much aware of the input and output associated with the computer. They submit input data to the computer to get processed information, the output.

Sometimes the output is an instant reaction to the input. Consider these examples:

·         Zebra-striped bar codes on supermarket items provide input that permits instant retrieval of outputs - price and item name - right at the checkout counter.

·         A bank teller queries the computer through the

2.  List the fundamental design issues in designing an instruction set.

Answer : The design of instruction sets is a complex issue. There were two stages in history for the microprocessor. The first was the CISC (Complex Instruction Set Computer), which had many different instructions. In the 1970s, however, places like IBM did research and found that many instructions in the set could be eliminated. The result was the RISC (Reduced Instruction Set Computer), an architecture that uses a smaller set of instructions. A simpler instruction set may offer the potential for higher speeds, reduced processor size, and reduced power consumption. However, a more complex set may optimize common operations, improve memory/cache efficiency, or simplify programming.

4. Briefly explain the read and write cycle of an 8086 processor.

Answer : The 8086 has a combined address and data bus commonly called as time multiplexed address and data bus. The main reason behind multiplexing address and data over the same pins is the maximum utilization of processor pins and it facilitates the use of 40 pin standard DIP package. The bus can be demultiplexed using a few latches and transceivers, whenever required.

Basically all the processor bus cycle consist of is at least four clock cycles. These are referred to as T1, T2, T3, T4. The address is transmitted by the processor during T1. It is present on the bus only for one cycle.The negative edge of t

5. Briefly explain Interrupt Driven I/O.

Answer : interrupt I/O A way of controlling input/output activity in which a peripheral or terminal that needs to make or receive a data transfer sends a signal that causes a program interrupt to be set. At a time appropriate to the priority level of the I/O interrupt, relative to the total interrupt system, the processor enters an interrupt service routine (ISR). The function of the routine will depend upon the system of interrupt levels and priorities that is implemented in the processor.

In a single-level single-priority system there is only a single I/O interrupt – the logical OR of all the connected I/O devices. The associated interrupt

6 What is the difference between Synchronous and Asynchronous Data Transfer?

Answer: Synchronous data transfer

Synchronous means "at the same time”. The device which sends data and the device which receives data are synchronized with the same clock. When the CPU and I/O devices match in speed, this technique of data transfer is employed. The data transfer with I/O devices is performed executing IN or OUT instructions for I/O mapped I/O devices or memory read/write instructions for memory mapped I/O devices. The IN instruction is used to read data from an input device or input port. The OUT instruction is used to send data from the

Dear students get fully solved assignments

Send your semester & Specialization name to our mail id :

“ help.mbaassignments@gmail.com ”

or

Call us at : 08263069601